Name :  Dr . S.P.Joy Vasantha Rani

Designation :  Professor

Educational Qualification :  M.E., Ph.D

Area of Specialization : VLSI, Signal processing, Reconfigurable Hardware architectures

Email ID :  This email address is being protected from spambots. You need JavaScript enabled to view it.

Phone : 044-22516240

 IRINS Profile

• Educational Qualifications

  Sl.No.	Examination Passed	Branch/Specialization	Year of Passing/ awarded	Institution where studied	University/ Board
  1)	PhD	VLSI	2009	Madras Institute of Technology, Anna University	Anna University
  2)	M.E	Power Electronics	1995	College of Engineering, Guindy, Anna University	Anna University
  3)	B.E	ECE	1993	Government College of Engineering, Tirunelveli, Madurai Kamaraj University	Madurai Kamaraj University

   

   

   

   

   

   

   

   

   

• Post Held

   

  Post Held	Period of Service		Name & Address of Employer
  	From	To
  Associate Professor	29-10-2015	Till date	MIT Campus, Anna University
  Assistant Professor	29-10-2008	28-10-2015	MIT Campus, Anna University
  Lecturer	8-7-2004	28-10-2008	MIT Campus, Anna University
  Teaching Research Associate	15-12-2000	7-7-2004	MIT Campus, Anna University
  Lecturer	19-7-1999	14-12-2000	Sri Muthukumaran Institute of Technology, Chennai-69
  Lecturer	26-6-1996	28-6-1999	National Engineering College, Kovilpatti

• Journals

   

  1. P., Joy Vasantha Rani, S.P., "Wire-Length and Run-Time Optimization in FPGA Placement Using Hybrid Iterative Algorithms", Journal of Circuits, Systems and Computers, published by World Scientific Publishers. Vol. 2150081, (2020).
  2. C, S.P.Joy Vasantha Rani, "Performance Analysis of Intrinsic Embedded Evolvable Hardware using Memetic and Genetic Algorithms", International Journal of Bio-Inspired Computation (IJBIC), published by Inderscience Publishers. Vol. 15, Issue 1, pp. 43-51 (2020).
  3. R, Joy Vasantha Rani S.P, "Nonlinear Controller: Voltage Controlled PFC-Based Fuzzy MDPSM Controller with Predictive Input Voltage", Journal of Circuits, Systems and Computers, published by World Scientific. Vol. 2050207, (2020).
  4. Senthil Sivakumar, S.P.Joy Vasantha Rani, "Time domain modelled ADC BIST with ramp noise projection", International Journal of Electronics, published by Taylor & Francis. Vol. 106, Issue 8, pp. 1127-1140 (2019).
  5. Senthil Sivakumar, SP Joy Vasantha Rani, "Efficient Design of ADC BIST with an Analog Ramp Signal Generation and Digital Error Estimation", Journal of Circuits, Systems and Computers, published by World Scientific. Vol. 28, Issue 3, pp. 1950042 (2019).
  6. C, SP Joy Vasantha Rani, "A Fast On-Chip Adaptive Genetic Algorithm Processor for Evolutionary FIR Filter Implementation Using Hardware–Software Co-Design", Journal of Circuits, Systems and Computers, published by World Scientific. (2019).
  7. Senthil Sivakumar & S.P.Joy Vasantha Rani, "Design of Linear Ramp Generator and Digital ORA for an area efficient high speed ADC BIST", Journal of Electrical Engineering, published by Politehnica Publishing House. (2018).
  8. Senthil Sivakumar, SP Joy Vasantha Rani, "An ADC BIST using on-chip ramp generation and digital ORA", Microelectronics Journal, published by Elsevier. Vol. 81, pp. 8-15 (2018).
  9. Senthil Sivakumar M and Joy Vasantha Rani.S.P."An area efficient, high-frequency digital built-in self-test for analogue to digital converter", International Journal of Electronics, 105:8, 1319-1330, DOI: 1080/00207217.2018.1440431 (2018)
  10. Indhumathi, S.P.Joy Vasantha Rani, "Remote fault diagnosis for distribution substation using Bayesian probabilistic matrix", Journal of Computational and Theoretical Nanoscience , published by American Scientific Publishers. Vol. 14, Issue 7, pp. 3463-3471 (2017).
  11. K, Joy Vasantha Rani.S.P and Kithikadevi. N, "Achievement of Cascaded Multirate FIR Filter Structures with CSE and CSD", Journal of Electrical Engineering, published by Politehnica Publishing House. Vol. 17, Issue 2, pp. 1 - 13 (2017).
  12. Prasanna, SC & Joy Vasantha Rani, SP, " Area and speed efficient implementation of symmetric FIR digital filter through reduced, parallel LUT decomposed DA approach", Circuits and Systems, published by Scientific Research Publishing. Vol. 7, Issue 8, pp. 1379-1391 (2016).
  13. S.C.Prasanna, S.P.Joy Vasantha Rani, " An efficient Implementation of Reconfigurable Interpolation Root-Raised Cosine FIR filter for SDR Application", Sadhana - AcademyProceedings in Engineering Science(Accepted), published by Springer. (2016).
  14. C.Ranjith, S.P.Joy Vasantha Rani, B.Priyadharshini, Medhuna Suresh and M.Madhusudhanan, "Optimizing GA operators for system evolution of Evolvable Embedded Hardware on Virtex 6 FPGA", ARPN journal of Engineering and applied sciences, Vol. 10, Issue 11, pp. 4908-4914 (2015).
  15. J.Britto Pari and S.P.Joy Vasantha Rani, "An optimized Architecture for Adaptive Digital Filter", ARPN journal of Engineering and applied sciences, Vol. 10, Issue 11, pp. 4964 - 4970 (2015).
  16. S.P.Joy Vasantha Rani, J.Samson and P.Vishak, "Dynamic Reconfigurable Architecture design of Viterbi Decoder", International journal of Applied Engineering Research, published by RIP Publications. Vol. 10, Issue 60, pp. 86 - 92 (2015).
  17. S.C.Prasanna and S.P.Joy Vasantha Rani, "Universal Programmable Modulator Architecture For Software Defined Radio", International journal of Applied Engineering Research, published by RIP Publications. Vol. 10, Issue 9, pp. 8854-8860 (2015).
  18. D.C.Diana, S.P.Joy Vasantharani, T.R. Nithya. and B.Srimukhee, "Adaptive Inertia Weight Particle Swarm Optimization For Linear and Nonlinear Channel Equalization", International Journal Of Scientific Research(IJSR), published by The Global Journals, India. Vol. 3, Issue 4, pp. 27-30 (2014).
  19. Britto Pari. J and Joy Vasantha Rani.S.P., "A Comparative Study on LUT and Accumulator Radix-4 Based Multichannel RNS FIR Filter Architectures", International Journal of Engineering and Technology (IJET), Vol. 6, Issue 2, pp. 735-744 (2014).
  20. Britto Pari. J and Joy Vasantha Rani.S.P., "Reconfigurable architecture of RNS based high speed FIR filter", Indian journal of Engineering and Material sciences(IJEMS), Vol. 21, pp. 233-240 (2014).
  21. Joy Vasantha Rani.S.P., "Pipelined Hardware design of Self Tuning Controller with On-chip Parameter Estimator", International journal of High Performance Systems Architecture (IJHPSA), published by Inderscience Publishers. (2014).
  22. Britto Pari. J and Joy Vasantha Rani.S.P., "FPGA Implementation of Adaptive Filter using Optimized Parallel FIR Filter ", International Journal of Computer Applications in Engineering, Technology and Sciences (IJ-CA-ETS) , Vol. 6, Issue 2, pp. 63-67 (2014).
  23. K.Mariammal, S.P.Joy Vasantha Rani and M.Banupriya, "Area Reduction using Farrow based Multirate Filter structure for Sampling rate conversion from CD to DAT", International journal of Applied Engineering Research, published by RIP Publications. Vol. 9, Issue 20, pp. 4722 - 4727 (2014).
  24. S.C.Prasanna and S.P.Joy Vasantha Rani, "Design of Transmitter for SDR application", International Journal of Advent research in Computer and Electronics (IJARCE), Vol. 1, Issue 7, pp. 36-42 (2014).
  25. S.P.Joy Vasantharani and K.Aruna Prabha, "Stochastic Logic Computation based RBFNN with Adaptive Hidden Layer Structure", Journal of Engineering, Design and Technology, published by Emarald publications. Vol. 8, pp. 206-220 (2010).
  26. S.P.Joy Vasantharani, P.Kanagasabapathy and L.Suganthi, " FPGA based Floating point Hardware design of recursive K-Means clustering algorithm for RBF neural network", International Journal of Intelligent Systems Technologies and Applications(IJISTA), published by Inderscience Publishers. Vol. 6, Issue 1, pp. 61-76 (2009).
  27. S.P.Joy Vasantharani, P.Kanagasabapathy, "Pipelined Floating Point hardware for Adaptive RBFNN Control", International journal of Systemics, Cybernetics and Informatics, pp. 23-30 (2008).

• Conferences

  1. Sudhanya, S.P.Joy Vasantha Rani, MC Lavanya, "Design of Logic Blocks for Efficient Architecture of FPGA" presented in a International level conference on IEEE 1st International Conference on Energy, Systems and Information Processing (ICESIP), organised by VIT Chennai, India from 04-Jul-2019 to 05-Jul-2019
  2. Thangam, S.P.Joy Vasantha Rani, "Voltage Controlled PFC Based Interleaved Synchronous Buck Converter BLDC motor" presented in a International level conference on 2019 IEEE 1st International Conference on Energy, Systems and Information Processing (ICESIP), India from 04-Jul-2019 to 05-Jul-2019.
  3. V.Karpagam, M.Senthil Sivakumar, S.P.Joy Vasantha Rani, "Effect of Ramp slope error in an on-chip ADC BIST" presented in a International level conference on 4th International conference on Science and Technology(ICONSET), organised by Jeppiar Engineering College, Chennai, India from 23-Mar-2018 to 24-Mar-2018.
  4. Jancy, Sudhanya.P, S.P.Joy Vasantha Rani, "Hybrid PSO-SA Algorithm for FPGA Placement" presented in a International level conference on 4th International Conference on Science and Technology(ICONSET), organised by Jeppiar Engineering College, Chennai, India from 23-Mar-2018 to 24-Mar-2018.
  5. Ashwini, M.Senthil Sivakumar, P.Joy Vasantha Rani, "Design of Linear Ramp Generator for ADC" presented in a International level conference on ICSCN -4th International Conference on Signal processing, Communication and Networking, organised by MIT, Chennai, India from 16-Mar-2017 to 18-Mar-2017.
  6. Jayashree, Ranjith.C, S.P.Joy Vasantha Rani, "A VLSI Implementation of an Adaptive Genetic Algorithm Processor" presented in a International level conference on ICSCN -4th International Conference on Signal processing, Communication and Networking, organised by MIT, Chennai, India from 16-Mar-2017 to 18-Mar-2017.
  7. Thangam, S.P.Joy Vasantha Rani, "Comparative analysis of PWM/PFM controlled SMPS using Matlab Simulink" presented in a International level conference on 4th International Conference on Signal Processing, Communication and Networking, ICSCN 2017, organised by Madras Institute of Technology, Chrompet, India from 16-Mar-2017 to 18-Mar-2017.
  8. Senthil Sivakumar, S.P. Joy Vasantha Rani, "Design of digital Built-In Self-Test for Analog to Digital Converter" presented in a International level conference on 10th International Conference on Intelligent Systems and Control (ISCO 2016), organised by Karpagam College of Engineering, Chennai,, India, pp.821-826 from 07-Jan-2016 to 08-Jan-2016.
  9. Krishnaveni, C. Ranjith and S.P. Joy Vasantha Rani, "Evolvable Hardware Architecture Using Genetic Algorithm for Distributed Arithmetic FIR Filter", Artificial Intelligence and Evolutionary Computations in Engineering Systems. Advances in Intelligent Systems and Computing, published by SPRINGER. Vol. 517, pp. 295-304 (2017).
  10. S, Senthil Sivakumar.M, S.P.Joy Vasantha Rani, "Design of Linear Ramp Generator for ADC" presented in a International level conference on ICSCN -4th International Conference on Signal processing, Communication and Networking, organised by MIT, Chennai, India from 16-Mar-2017 to 18-Mar-2017.
  11. Senthil Sivakumar and S. P. Joy Vasantha Rani, "Design of digital Built-In Self-Test for Analog to Digital Converter" presented in a International level conference on 10th International Conference on Intelligent Systems and Control (ISCO 2016), organised by Karpagam College of Engineering, Chennai,, India, pp.821-826 from 07-Jan-2016 to 08-Jan-2016.
  12. C.Ranjith and S.P.Joy Vasantha Rani, "A Hardware Implementation of Evolvable Embedded System for Combinational Logic Circuits using Virtex 6 FPGA" presented in a International level conference on 1st International Conference on Nano- electronics, Circuits and Communication Systems (NCCS – 2015), organised by ARTTC, BSNL, Ranchi, Jharkhand, India from 09-May-2015 to 10-May-2015.
  13.  D.C. Diana and S.P.Joy Vasantha Rani, "Modified PSO based Equalizers for Channel Equalization" presented in a International level conference on 1st International Conference on Nano- electronics, Circuits and Communication Systems (NCCS – 2015), organised by ARTTC, BSNL, Ranchi, Jharkhand, India from 09-May-2015 to 10-May-2015.
  14. K.Mariammal, S.P.Joy Vasantharani,, "Design and analysis of Fast convolution based Multirate Filter Banks" presented in a International level conference on 1st International Conference on Nano-electronics, Circuits and Communication Systems (NCCS – 2015), organised by ARTTC, BSNL, Ranchi, Jharkhand, India from 09-May-2015 to 10-May-2015.
  15. S.P.Joy Vasantha Rani, Samson, Vishak, "Dynamic Reconfigurable architecture design of Viterbi Decoder" presented in a International level conference on International conference on Architecture Software systems and Green Computing, organised by AVIT, Chennai, India from 07-May-2015 to 08-May-2015.
  16. C.Indumathi and S.P.Joy Vasantha Rani, "A Fuzzy based Fault Type Detector for Remote Fault diagnosis of Distribution Feeders" presented in a International level conference on 3rd International Conference on Signal processing, Communication and Networking (ICSCN), organised by MIT, Chrompet, India from 26-Mar-2015 to 28-Mar-2015.
  17.  J.Britto Pari, S.P.Joy Vasantha Rani, "FPGA Realization of Multiplierless FIR filter Architectures" presented in a International level conference on 3rd International Conference on Signal processing, Communication and Networking (ICSCN), organised by MIT, Chrompet, India from 26-Mar-2015 to 28-Mar-2015.
  18.  K.Mariammal, S.P.Joy Vasantharani,, "Hardware Implementation of Speech Recognition and validation using Arduino Leonardo Board" presented in a International level conference on International Conference on Emerging Trends in Information Technology(ICETIT’15), India from 09-Mar-2015 to 10-Mar-2015.
  19. "Evolvable Hardware: A New Trend in the Design of Digital VLSI Systems" presented in a International level conference on 8th International Conference on Advanced Computing and Communication Technologies (ICACCT-2014), India from 05-May-2014.
  20.  S.Balamurali, S.P.Joy Vasantha Rani, "LUT based design of Adaptive Filter for Digital Hearing Aid applications" presented in a International level conference on International conference on Computer science and Engg(ICCSE), India from 14-Apr-2014 to 15-Apr-2014.
  21. D.C. Diana and S.P. Joy Vasantha Rani, "Improved Particle Swarm Optimization Algorithm for Adaptive Equalization" presented in a International level conference on International Conference on Mathematical Computer Engineering, organised by VIT, Chennai, India from 29-Nov-2013 to 30-Nov-2013.
  22. K.Mariammal, S.P.Joy Vasantha Rani and T.Kohila, "Area efficient high speed low power multiplier architecture for multirate filter design" presented in a International level conference on IEEE International conference on Emerging Trends in Computing, Communication and Nanotechnology, India from 25-Mar-2013 to 26-Mar-2013.
  23.  J.Britto Pari, S.P.Joy Vasantha Rani, "Reconfigurable RNS FIR filter Using Higher Radix Multiplier" presented in a International level workshop on Third International Workshop on VLSI (VLSI 2012), Chennai, India from 13-Jul-2012 to 15-Jul-2012.
  24. Harish, S. and Joy Vasantha Rani.S.P., "A dynamic partial reconfigurable FIR filter architecture" presented in a International level conference on International Conference on Recent Trends In Information Technology (ICRTIT), organised by MIT, India from 19-Apr-2012 to 21-Apr-2012.
  25.  Katna Radha and S.P.Joy Vasantha Rani, "High speed Reed Solomon decoder using Galois field Arithmetics" presented in a National level conference on Proceedings of National Conference on Signal Processing, Communications and VLSI design (NCSCV'09), India from 22-May-2009 to 24-May-2009.
  26.  Aruna Prabha K., Joy Vasantha Rani S.P., "Hardware implementation of RBF neural network algorithms integrated with stochastic logic theory for control applications" presented in a International level conference on System analysis and information technologies: Materials of the X International Conference on Science and Technology, Kyiv, Ukraine from 20-May-2008 to 24-May-2008.
  27.  S.P.Joy Vasantha Rani, P.Kanagasabapathy, "Pipelined Floating-point Hardware of On-chip Parameter Estimator for Self Tuning Control" presented in a International level conference on Sensors, Signal Processing,Communication, control and Instrumentation(SSPCCIN), organised by Vishwakarma Institute of Technology, Pune, India from 03-Jan-2008 to 05-Jan-2008.
  28.  S.P.Joy Vasantha Rani, P.Kanagasabapathy, "Multilayer perceptron neural network architecture using VHDL with combinational logic Design of Sigmoid Function" presented in a International level conference on ICSCN, organised by MIT, India from 22-Feb-2007 to 24-Feb-2007.
  29. organised by CEG, Anna University, India from 01-Jun-2006 to 02-Jun-2006.
  30. S.P.Joy Vasantha Rani, P.Kanagasabapathy, "Digital Fuzzy logic controller using VHDL" presented in a International level conference on INDICON, organised by IIT, Chennai, India from 11-Dec-2005 to 13-Dec-2005.
  31. Joy Vasantha Rani S.P., Kanagasabapathy.P, "Design of Neural Network on FPGA" presented in a International level conference on International Conference on VLSI (VLSI’04), Las Vegas, Neveda,USA from 21-Jun-2004 to 24-Jun-2004.
  32. L.Suganthi, S.P.Joy Vasantha Rani, "Floating point hardware architecture of RBF neural network for adaptive control applications" presented in a National level conference on National conference on Information, communication and computing(NCICC'2007), organised by CEG campus, India .
  33. T.Anbanandhan, S.P.Joy Vasantha Rani, "High speed parallel implementation of current mode multiplier/divider for signal processing applications" presented in a National level conference on National conference on Information, communication and computing(NCICC'2007), organised by CEG campus, India . 

• Invited Lectures

  1. Delivered a Lecture on "Designing Arithmetic Building Blocks" in FDTP on VLSI Design-EC6601 organized by Department of Electronics Engineering, MIT, Chennai (24-Nov-2017).
  2. Delivered a Lecture on "Embedded SOC platform on FPGA" in Workshop on "EMBEDDED SOC DESIGN" organized by Department of Electronics Engineering, MIT Campus,, Chrompet, Chennai (08-Mar-2016).
  3. Delivered a Lecture on "CMOS Technology and HDL Programming" in Guest Lecture for students organized by Vel Tech Rangarajan Dr.Sagunthala R&D Institute of, Chennai (16-Oct-2015).
  4. Delivered a Lecture on "Microprocessors and Microcontrollers" in FDP Programme organized by Sri Sastha Institute of Engineering and Technology, Chennai (16-Jun-2014).
  5. Delivered a Lecture on "Sequential Circuits" organized by RMK Engineering College, Chennai (16-Feb-2013).
  6. Delivered a Lecture on "Realization of FIR filters" in FDTP on EC2302 Digital Signal Processing organized by Department of Electronics Engineering, MIT campus, Chrompet (17-Jun-2013).
  7. Delivered a Lecture on "DFT and its properties" in FDTP on EC2302 Digital Signal Processing organized by Department of Electronics Engineering, MIT campus, Chrompet (19-Jun-2013).
  8. Delivered a Lecture on "Digital Principles and Digital VLSI" in Guest Lecture organized by University College of Engineering, Tindivanam, India (25-Oct-2012).

• Programme Organised

  1. Coordinator, National level workshop on "UGC Sponsored Two Days Workshop On “Embedded SOC Design"" from 07-Mar-2016 to 08-Mar-2016.
  2. Coordinator, National level Short Course on "FDTP on VLSI Design" from 09-Dec-2013 to 15-Dec-2013.
  3. Coordinator, National level workshop on ""Two days workshop on "Analog IC design"" from 14-Sep-2012 to 15-Sep-2012.
  4. Coordinator, National level workshop on "Two days workshop on "Development of Embedded system using C for ARM with extensive hands on Experience"" from 07-Jan-2010 to 08-Jan-2010. 

• Programme Attended

  27. Participated in a National level workshop on "Advanced Digital Design Flow using Cadence" organized by MIT Chennai, India from 01-Mar-2018 to 03-Mar-2018.

  26. Participated in a National level workshop on "One week Short term course on "Professional Ethics and Values"" organized by NITTTR, Chennai, India from 27-Nov-2017 to 01-Dec-2017.

  25. Participated in a International level workshop on "FDP on Student Evaluation and Question Paper Setting" organized by MIT Campus, Anna University, India from 13-Oct-2016 to 15-Oct-2016.

  24. Participated in a International level conference on "International conference on Architecture, Software systems and Green computing(ICASG 2015)" organized by AVIT, Chennai, India from 07-May-2015 to 08-May-2015.

  23. Participated in a National level workshop on "Advancements in Biomedical Signal and Image Processing (UGC-DRS-II(SAP-II) sponsored)" organized by Dept. of Electronics Engineering, MIT campus, Anna University, India from 29-Oct-2015 to 30-Oct-2015.

  22. Attended a International level Short Course on "Two week ISTE STTP on "Introduction to Design of Algorithms"" organized by IIT, Kharagpur, India from 27-Apr-2015 to 30-May-2015.  

  21. Participated in a International level conference on "3rd International Conference on Signal processing, Communication and Networking (ICSCN)" organized by MIT, Chrompet, India from 26-Mar-2015 to 28-Mar-2015.

  20. Participated in a National level workshop on "Image Processing framework using FPGA" organized by MIT, India from 15-Oct-2012 to 16-Oct-2012.

  19. Participated in a National level workshop on "Basic Electronics" organized by IIT, Bombay, India from 28-Jun-2011 to 08-Jul-2011.

  18. Participated in a National level workshop on "E-Learning for Engineering Educators" organized by MIT, India from 24-Jun-2011 to 25-Jun-2011.

  17. Participated in a National level workshop on "VLSI for signal processing" organized by MIT, India from 14-Mar-2011 to 15-Mar-2011.

  16. Attended a National level seminar on "Guidelines to sponsored research projects" organized by Dhanalakshmi Engineering college, India from 06-May-2010.

  15. Participated in a National level workshop on "Effective teaching/ learning of computer programming" organized by IIT, Bombay, India from 14-Dec-2009 to 24-Dec-2009.

  14. Participated in a International level conference on "International conference on Advanced computing" organized by MIT, India from 13-Dec-2009.

  13. Attended a National level Short Course on "Faculty development training program on Web technology" organized by MIT, India from 01-Dec-2009 to 07-Dec-2009.

  12. Participated in a National level workshop on "high speed digital design and testing" organized by MIT, India from 23-Oct-2009. 11. Participated in a International level workshop on "Content based image retrieval and fusion" organized by MIT, India from 07-Aug-2009 to 09-Aug-2009.

  10. Participated in a International level conference on "Intelligent agent and multi-agent systems" organized by AVIT, India from 22-Jul-2009 to 24-Jul-2009.

  9. Participated in a National level workshop on "Embedded Systems Development on FPGAs" organized by MIT, India from 07-Jan-2008 to 08-Jan-2008.

  8. Participated in a International level conference on "International Conference on Sensors, Signal Processing, Communication, Control and Instrumentation (SSPCCIN) " organized by Vishwagarma Institute of Technology, Pune, India from 03-Jan-2008 to 05-Jan-2008.

  7. Attended a National level Short Course on "Training Program on ARM Processor based Development System" organized by MIT, India from 23-May-2007 to 24-May-2007.

  6. Participated in a International level conference on "International Conference on Signal Processing, Communication and Networking(ICSCN)" organized by MIT, India from 22-Feb-2007 to 24-Feb-2007.

  5. Participated in a National level workshop on "Continuing Education Programme on Embedded systems and technology" organized by IIT, Karagpur, India from 19-Jun-2006 to 24-Jun-2006.

  4. Participated in a National level conference on "2nd National Conference on Signals, systems and Communication(NCSSC)" organized by Department of ECE, CEG campus, Anna University, India from 01-Jun-2006 to 02-Jun-2006.

  3. Participated in a International level conference on "International Conference INDICON " organized by IEEE Madras section at IIT Madras, India from 11-Dec-2005 to 13-Dec-2005.

  2. Attended a National level Short Course on "A refresher course on VLSI design" organized by MIT, India from 28-Mar-2005 to 29-Mar-2005.

  1. Attended a National level Short Course on "AICTE-ISTE Short term training programme on Trend in Intelligent Measurement and control" organized by MIT from 22-Nov-2004 to 27-Nov-2004.

   

   

• Membership

  MEMBERSHIP IN PROFESSIONAL ORGANIZATION

  • ISTE
  • IETE

• Research Guidance

  Ph.D completed as supervisor : 8

  Ph.D on going as Supervisor : 1

  Ph.D on going as Joint supervisor : 2

   

  Sl.No	Name of the Scholar	Topic	Mode	Year of completion
  1.	J.Britto Pari	Efficient digital filter architectures for multichannel filtering and adaptive filtering techniques	Full Time	2016
  2.	D.C.Diana	Investigation of Swarm Intelligence techniques to enhance Channel Equalization	Part Time	2017
  3.	S.C.Prasanna	Reconfigurable and dedicated FIR filters, Interpolators and modulators for SDR	Part Time	2017
  4.	K.Mariammal	Multiplierless Implementation of Area Efficient Multirate FIR filter structures for Sampling Rate Conversion	Part Time	2018
  5.	M.Senthil Sivakumar	Design of Built-In Self-Test for Analog to Digital Converter with Static Error Modeling and Calibration	Full Time	2019
  6.	C. Indhumathi	Intelligent Fault Location, Isolation and Service Restoration in Distribution System	Part Time	2019
  7.	R.Thangam	Digital Pulse Skipping Modulation Strategies for DC-DC Converters to improve the Power Conversion Efficiency at Partially Loaded Conditions and incorporation of PFC	Part Time	2020
  8.	Ranjith C	Embedded Evolvable Hardware Design of Digital Circuits using Bio-inspired Algorithms	Part Time	2020
  9.	P.Sudhanya	Efficiency Enhancement of FPGA Architecture	Full Time	On Roll

   

   

• Subjects Handled

  PG Subjects:

  • Design For Testability
  • VLSI Architectures for System Design
  • Hardware – Software Codesign for Embedded system
  • VLSI for Signal Processing
  • PC and Microcontroller based system Design

  UG Subjects:

  • Digital System Design
  • VLSI Design
  • Microprocessors and Microcontrollers
  • Computer Architecture and Organisation
  • Digital Electronics for system Design
  • Electronics Circuits II
  • Power Electronics
  • Advanced Microprocessors
  • Analog Electronics

• Projects Undertaken

  1. “Performance Enhancement in FPGA Architecture by Efficient design of Logoc Blocks” sponsored by DST – Women Scientist Scheme A(WOS - A), 2018-2021. Scientist Mentor: Dr.S.P.Joy Vasantha Rani, Associate Professor. Principal Investigator: Ms.P. Sudhanya, Research Scholar, Dept of Electronics Engineering, MIT Campus. Project Cost: 17.8 Lakhs.
  2. "Sound of Actions – A Technical Aid for Speaking Disabled", funded by CTDT Research Support Scheme by Anna University (Mar. 2014 - Dec. 2014).. Project Cost: 25000.00.
  3. "Harassment Emergency Rescuer(HER)", funded by CTDT Research Support Scheme by Anna University (Mar. 2015 - Dec. 2015).. Project Cost: 25000.00.
  4. "FPGA based real time visual static hand gesture recognition system", funded by CTDT Research Support Scheme by Anna University (Mar. 2016 - Dec. 2016) (December-1969 - December-1969). Project Cost: 25000.00.

• Additional Responsibilities

  Institute level:

  • Deputy Warden, Girls Hostel, Anna University, Chennai from May-2019.
  • Selection Committee Member To Recruit Project staff, Sponsored Projects, CTDT, 2015-2016, Anna University, Chennai.
  • Additional Chief Superintendent for end semester examinations for UG students during Apr./May 2010.

  Department level:

  • Department NAAC Coordinator, Department of Electronics Engineering, Anna University, Chennai from May-2019.
  • IQAC Department Coordinator, Department of Electronics Engineering, Anna University, Chennai from May-2019.
  • Syllabus committee member of M.E. VLSI design and Embedded system (2015 CBCS Regulation) and contributed in framing the curriculum and the syllabus.
  • Departmental Consultative Committee (DCC) member in the dept. of Electronics Engineering, 2012-2015
  • Purchased FPGA development boards and testing equipments worth Rs. 35 Lakhs – under  DST-FIST 2012-2017
  • Guiding UG  and PG project students.
  • Class committee chairman for UG students from 2012 - 2016.
  • UG Syllabus Revision Committee Member for 2012 regulation.
  • Involved in purchase activities for purchasing VLSI products, Microprocessors and microcontrollers during 2011.
  • President of Electronics Engineering Association (EEA) in the academic year 2009-10. On behalf of the EEA, six workshops have been organized for students during Electrofocus 2010.
  • Faculty advisor for NRI students in the academic year 2009-10.